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基于MCF51CN128设计的以太网连接参考方案
发布时间:2017-03-17 阅读：次 [打印文章] [关闭窗口]The MCF51CN128 features the following functional units:
• 32-bit ColdFire V1 Central Processing Unit (CPU)
– Up to 50.33 MHz ColdFire CPU from 3.6 V to 3.0 V, up to 40 MHz CPU from 3.0 V to 2.1 V, and up to 20 MHz CPU from 2.1 V to 1.8 V across temperature range of –40 °C to 85 °C
– Provides 0.94 Dhrystone 2.1 MIPS per MHz performance when running from internal RAM (0.76 DMIPS/MHz from flash)
– ColdFire Instruction Set Revision C (ISA_C)
– Support for up to 45 peripheral interrupt requests and 7 software interrupts
• On-Chip Memory
– 128 KB Flash, 24 KB RAM
– Flash read/program/erase over full operating voltage and temperature
– On-chip memory aliased to create a contiguous memory扁平型电感 space with off-chip memory
– Security circuitry to prevent unauthorized access to Peripherals, RAM, and flash contents
• Ethernet
– FEC—10/100 BASE-T/TX, bus-mastering fast Ethernet controller with direct memory access (DMA); supports half or full duplex; operation is limited to 3.0 V to 3.6 V
– MII—media independent interface to connect Ethernet controller to external PHY; includes output clock for external PHY
• External Bus
– Mini-FlexBus—Multi-function external bus interface; supports up to 1 MB memories, gate-array logic, simple slave device or glueless interfaces to standard chip-selected asynchronous memories
– Programmable options: access time per chip select, burst and burst-inhibited transfers per chip select, transfer direction, and address setup and hold times
• Power-Saving Modes
– Two low-power stop modes, one of which allows limited use of some peripherals (ADC, KBI, RTC)
– Reduced-power wait mode shuts off CPU and allows full use of all peripherals; FEC can remain active and conduct DMA transfers to RAM and assert an interrupt to wake up the CPU upon completion
– Low-power run and wait modes allow peripherals to run while the voltage regulator is in standby
– Peripheral clock enable register can disable clocks to unused modules, thereby reducing currents
– Low-power external oscillator that can be used in stop3 mode to provide accurate clock source to active peripherals
– Low-power real-time counter for use in run, wait, and stop modes with internal and external clock sources
– 6 μs typical wake-up time from stop3 mode
– Pins and clocks to peripherals not available in smaller packages are automatically disabled for reduced current consumption; no user interaction is needed
• Clock电感器生产厂家 Source Options
– Oscillator (XOSC) — Loop-control pierce oscillator; crystal or ceramic resonator range of 31.25 kHz to 38.4 kHz or 1 MHz to 25 MHz
– Multi-Purpose Clock Generator (MCG) — Flexible clock source module with either frequency-locked-loop (FLL) or phase-lock loop (PLL) clock options. FLL can be controlled by internal or external reference and includes precision trimming of internal reference, allowing 0.2% resolution and 2% deviation over temperature and voltage. PLL derives a higher acc台庆电感uracy clock source derived by an external reference
• System Protection
– Watchdog computer operating properly (COP) reset with option to run from dedicated 1-kHz internal clock source or bus clock
– Low-voltage detection with reset or interrupt; selectable trip points
– Illegal opcode and illegal address detection with programmable reset or exception response
– Flash block protection
• Development Support
– Single-wire background debug module (BDM) interface; supports same electrical interface used by the S08, 9S12, and 9S12x families debug modules
– 4 PC plus 2 address (optional data) breakpoint registers with programmable 1- or 2-level trigger response
– 工字电感器64-entry processor status and debug data trace buffer with programmable start/stop conditions
• Peripherals
– ADC—Up to 12 channel, 12-bit resolution; 2.5 μs conversion time; automatic compare function; 1.7 mV/°C temperature sensor; internal bandgap reference channel; operation in stop3; fully functional from 3.6 V to 1.8 V
– SCI—Three modules with optional 13-bit break
– SPI—Two interfaces with full-duplex or single-wire bi-directional; double-buffered transmit and receive; master or slave mode; MSB-first or LSB-first shifting
– IIC—Two IICs with up to 100 kbps with maxmimum bus loading; multi-master operation; programmable slave address; interrupt-driven byte-by-byte data transfer; supports broadcast mode and 11-bit addressing
– TPM—Two 3-channel, 16-bit resolution modules; selectable input capture, output compare, or buffered edge- or center-aligned PWM on each channel
– RTC—8-bit modulus counter with binary- or decimal-based prescaler; external clock source for precise time base, time-of-day, calendar- or task-scheduling functions; fr
PCB被动组件的隐藏行为和特性分析 文章摘自：凌力尔特技术论坛-与非网（https://linear.专注于大电流电感设计、制造：电话 ：181-2638-2251/module/forum/thread-593971-1-1.html）
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德州仪器 (TI）近日宣布推出业界首款 12-V，10-A，10-MHz 串联电容降压转换器，电流密度超过基于FPGA实现的CPCI数据通信本文设计的系统采用PLX公司生产的CPCI协议转换芯片PCI9054，通过Verilog HDL语言在FPGA中产生相应的控制信号，完成对数据的快速读写，从而实现了与CPCI总线的高速数据通信。高速数
